The FASTBUS Model 1881M contains 64 channels of analog-to-digital converter
(ADC) with current integrating inputs, and 13-bit resolution. These gated integrating
ADCs can be used to encode photomultiplier and chamber signals or to sample
slowly varying signals. DC-coupled gated integrators are best suited to high
rate applica tions, especially when a wide dynamic range is required.
The 1881M has been designed for short conversion time, maximum data throughput and short dead time, as required in state-of-the-art physics experiments. Data can be compacted (zero suppressed) through on-board circuitry to reduce data volume and transfer time. The 1881M contains a multiple event buffer which can store up to 64 events. This buffer can be read out at up to 10 megawords/sec, substantially reducing the dead time of the data acquisition system.
The 64 inputs are accepted via standard double row headers often used with mass terminated cables.
1881M Block Diagram
The 1881M ADC circuit is based on two LeCroy custom monolithics, an MQT200S
charge-to-time converter followed by an MTD133B time-to-digital converter, using
the linear Wilkinson run-down technique.
The MQT200S and an external capacitor form a integrator circuit which is active
during the gate period. At the termination of the gate the integrated charge
is removed from the capacitor by a constant current source within the MQT200S
producing an output pulse, the duration of which is proportional to the input
charge. This time duration is measured by the MTD133B. The high resolution of
the MTD133B permits the accurate conversion of a wide range of values. The 1881M
guarantees a linear range of 8192 codes above the pedestal in 13-bit mode (see
Figure 1) with typically ±7% differential non-linearities (see Figure 2).
Data translation and transfer times of the MTD133B produce a total conversion
time of 12 µsec.
Figure 1
Figure 2
Sparse data readout is a scheme which can be used to remove unwanted data from the module, for example, the background digitized when no pulse arrives on a channel during the gate. The 1881M allows the user to specify a set of 64 constants (one for each channel) which can be compared to the measurements. Only data exceeding these individual thresholds is included in the event data buffer. The sparse data readout feature can dramatically reduce the quantity of data which must be transferred over FASTBUS to the computer for processing (see Figure 3).
Figure 3
The module supports readout during conversion of earlier events from the buffer with no penalty in conversion time or FASTBUS performance. There is a slight increase in ADC noise. When readout is done during conver sion, a typical performance is 1.2 counts R.M.S.
The 1881M contains self test circuits allowing the operation of all ADC
channels to be verified. The self test circuits are voltage-programmed pulse
generators. A DC level (TEST REF) is bused from the 1810 CAT module to all
modules within the FASTBUS crate using the FASTBUS UR lines. When the module
is gated via CSR 0, the leading edge of the Gate causes a well defined charge
(proportional to the TEST REF Level) to be deposited in each of the inputs.
Addressing Modes: Geographic, Logical, and Broadcast (all classes).
Implemented Registers, FIFO.
Implemented Addressing Modes: Logical (16 bits), Geographical, Broadcast.
AS-AK Handshake Time: 125 nsec typical, 150 nsec maximum.
DS-DK Handshake Time: 65 nsec typical, 75 nsec maximum.
Module Identification Code: 104Fh.
Control and Status Registers
CSR 0h - Module ID and control status.
CSR 1h - FCW settings and gate and clear routing.
CSR 3h - Logical address.
CSR 5h - Word count for block transfers (automatically loaded by LOAD NEXT EVENT
command (CSR0 bit 8)).
CSR 7h - Broadcast class.
CSR 10h - Read\writeable pointers to circular buffer automatically advanced
by incoming events and LOAD NEXT EVENT command.
CSR C0000000h- Sparsification thresholds one per channel.
CSR C000003Fh
Slave Status Responses to Data Cycles:
SS Significance
0 = Valid Action
2 = End of Data
7 = Error. Invalid Secondary Address loaded into internal address register.
Implemented Broadcast Functions
Code Significance Comments
01h* - General Broadcast Select: The 1881M modules are selected and respond
to subsequent data cycles.
X5h - Class N Broadcast: The 1881M with class bit X set are selected and respond
to subsequent data cycles.
09h - Sparse Data Scan: 1881M modules containing at least one event assert the
T pin on the following read data cycle.
0Dh - All Device Scan: All 1881M modules assert their T pin on the following
read data cycle.
BDh - ADC Sparse Data Scan: Unique Sparse Data Scan for 1880 Series modules
only. Follows standard Sparse Data Scan (see above).
CDh - ADC Data Scan: Second level sparse data scan for 1881/1881M modules. ADCs
with at least one data word above threshold for the current event waiting to
be read out will assert T pin.
* An h subscript indicates hexadecimal (base 16).